北加州清华新闻 Tsinghua NorCal News: 2010/03

2010/03/30

[Tsinghua-NC] Taipei Nankang IC Design Incubation Center Silicon Valley Event 4/19 -- 4/23 2010 at ITRI International

You are cordially invited to the Taipei Nankang IC Design Incubation Center Silicon Valley Event 2010. (台北「南港IC設計育成中心2010年矽谷招商會」!

台北「南港IC設計育成中心」將於 4/19 - 4/23 在矽谷舉辦招商說明會，歡迎有意回台灣設立公司之廠商或創業團隊報名參加。該中心由經濟部於2003年10月設立，協助IC設計新創業者規劃全方位的IC營運環境，包含財務、法律、會計、技術及管理等專業諮詢、EDA軟體租賃、運算中心支援服務及資金面和人才面的資源協助等，為全台IC設計領域專屬之育成中心。

招募對象：中小型IC設計相關企業IC 設計廠商或創業團隊 (有意於台成立子公司或將營運總部移至台灣)

公開招商說明會：4/19 (Monday) 10:00 am -- 12:00 pm (僅此一場，敬請把握。)

個別廠商或創業團隊面談會議： 4/19(Monday) ~ 4/23 (Friday) 10:00 am -- 6:00 pm (每場一小時，請預約時段。)

招商說明會及面談會議地點： ITRI International, Inc., 2870 Zanker Road, Suite 140, San Jose, CA 95134

報名請洽： Yuping Chen (ypchen@itri.com) TEL：(408) 428-9988 ext. 19

本次招商活動亦安排專業會計師隨行，可提供台灣地區會計/稅務/工商登記等初步諮詢。

欲知更多詳情請參訪網站：

The Nankang Center home page

http://www.nspark.org.tw

The 2010 Silicon Valley event

http://www.nspark.org.tw/promo/recruiting.htm

__._,_.___

Reply to sender | Reply to group | Reply via web post | Start a New Topic

Messages in this topic (1)

Recent Activity:

New Members 1

Visit Your Group

----------------------------------------------------
Tsinghua Alumni Association, Northern California
http://www.tsinghua-nc.org

THAA-NC Forum: http://www.tsinghua-nc.org/forum

To subscribe to this group, send an email to:
tsinghua-nc-subscribe@yahoogroups.com----------------------------------------------------

MARKETPLACE

Do More for Dogs Group. Connect with other dog owners who do more.

Welcome to Mom Connection! Share stories, news and more with moms like you.

Hobbies & Activities Zone: Find others who share your passions! Explore new interests.

Switch to: Text-Only, Daily Digest • Unsubscribe • Terms of Use

__,_._,___

2010/03/22

[Tsinghua-NC] 4/4,7 清华大学“百年校庆”百名教授及学生文艺社团访问硅谷

百年清华，中西合璧，华夏增辉！莘莘学子，"自强不息，厚德载物"！

北京清华校长顾秉林院士亲自带队，包括清华大学各学院院长在内的、近百名知名教授和学生文艺社团将于四月四日至九日访问旧金山湾区。

在美丽清华园迎来百年华诞之际，与来自母校的老师、同学、朋友共同掀起北美庆典的序幕！

共度欢乐时光，见证骄傲时刻！

我们将为您带来两场盛大活动：

1."百年清华，百名教授" 盛大欢迎晚宴

四月四日（星期日）晚六点 April 4th (Sunday) 6:00PM

王朝魚翅海鮮酒家（Dynasty Chinese Seafood Restaurant）

10123 North Wolfe Road, #1688, Cupertino, CA

********************************************************************************

清华大学教授代表团
点击查看清华大学教授名单

********************************************************************************

2. "百年清华，硅谷之夜"清华大学艺术团文艺演出

四月七日（星期三）晚七点半 April 7th (Wed) 7:30PM

Flint Center for the Performing Arts

21250 Stevens Creek Blvd, Cupertino, CA 95014

********************************************************************************
清华大学艺术团简介
清华大学艺术团成立于1958年,辖军乐队、民乐队、合唱队、交响乐队、舞蹈队、话剧队、国际标准舞队、键盘队、美术社、京剧队、曲艺队等十一支队伍，拥有近千名成员。2009年11月，清华大学艺术团在北京人民大会堂，为奥巴马总统演出。2009年，为了庆祝共和国六十周年华诞，艺术团应邀参与了大型音乐舞蹈史诗《复兴之路》的排演工作，在人民大会堂连续演出数十场，并受到了国家领导人的亲切接见。在数次国家最高级别的艺术汇演或比赛中共获得一等奖一百余个。

********************************************************************************

点击此处预约"百年清华"活动

主办单位：

硅谷清华联网 (Silicon Valley Tsinghua Network)

北加州清华校友会 (Tsinghua Alumni Association of Northern California)

清华企业家协会 (Tsinghua Entrepreneur and Executive Club )

清华杰出青少年计划 (Tsinghua Youth Distinguished Program )

美中高层次人才交流协会 (US-China Association of High-level Professional )

浙江清华长三角研究院-硅谷创业基地

深圳清华大学研究院-北美创新创业中心

__._,_.___

Reply to sender | Reply to group | Reply via web post | Start a New Topic

Messages in this topic (1)

Recent Activity:

New Members 2

Visit Your Group

Switch to: Text-Only, Daily Digest • Unsubscribe • Terms of Use

__,_._,___

[Tsinghua-NC] Job opening at WD, San Jose

WD San Jose is looking for a condidate of FEA Analyst. See job description below. Email to qiangy@gmail.com if you are interested. Thanks.

-------------------------------------------------------

Job Title: FEA Analyst / Resonance FA - Mechanical Design

Position Type: Full Time

Department: Analysis/Resonance Dept

State: California;

City: San Jose

Job Description:

The engineer in this position will be responsible for the ACA resonance FA and HDI issues, who will extensively conduct Resonance and HDI problem FA with modeling and experimental approaches. This position also support new modeling and engineering efforts in the areas of HDI, Helium retention analysis, thermal analysis, flow dynamics, BP and top cover distortion, screw cleanness analysis, etc.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

·        Perform extensive FE resonance modeling using self-developed in-house tools, MATLAB, ANSYS and ANSYS Workbench;

·        Conduct the root cause diagnosis /FA on resonance, dynamics, HDI other solid mechanics related issues;

·        Support advanced mechanical and staging projects, such as Helium retention analysis and engineering work;

·        Interpret the FEA results and provide the physics of root causes and solutions;

·        Actively participate in group brain-storms and technical activities

·        Recommend design directions to meet product performance requirements during development and firefighting stages

Job Requirements:

·        At least 2 ~ 5 year professional ANSYS and DSP (digital signal process and analysis) experience;

·        PhD or Master in Mechanical Engineering or other related field is preferred;

·        Solid background skills in the areas of FEA, solid mechanics, dynamics, vibration, shock analysis, dynamic signal measurement, flow dynamics and so on.

·        Analysis and problem solving skills.

__._,_.___

Reply to sender | Reply to group | Reply via web post | Start a New Topic

Messages in this topic (1)

Recent Activity:

New Members 1

Visit Your Group

Switch to: Text-Only, Daily Digest • Unsubscribe • Terms of Use

__,_._,___

2010/03/18

[Tsinghua-NC] job opening for Senior ASIC / Methodology Engineer

Hi,

Here is another opening for Senior ASIC / Methodology Engineer.

Hongjian

Job title	Senior ASIC / Methodology Engineer
Location	San Jose, California
Country	USA

Job type	Full Time, Permanent
Job description	Senior ASIC / Methodology Engineer

As a senior member of our ASIC team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on such tasks as: netlist manipulation, clocks, timing convergence, design for test, and low power operation. Specifically you' be focusing on methodologies for full chip layout planning (partitioning, planning clock distribution, power control and other structures), full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic.

Responsibilities:

Develop advanced methodologies for synthesis, chip level integration, floorplanning, physical partitioning, and low power design flow (CPF/UPF)
Develop configurable timing flows using commercial timing tools for timing analysis and closure
Develop scripts for performing ECO's.
Collaborate and deploy methodologies for advanced design architectures.

Qualifications / Requirements:

Bachelor's, Electrical Engineering or BS/MS Electrical Engineering
Minimum 10 years experience with low power design methodology.
Experience with Synthesis and STA tools.
Experience with DFT tools
Strong scripting skills

__._,_.___

Reply to sender | Reply to group | Reply via web post | Start a New Topic

Messages in this topic (1)

Recent Activity:

New Members 6

Visit Your Group

MARKETPLACE

Do More for Dogs Group. Connect with other dog owners who do more.

Welcome to Mom Connection! Share stories, news and more with moms like you.

Hobbies & Activities Zone: Find others who share your passions! Explore new interests.

Switch to: Text-Only, Daily Digest • Unsubscribe • Terms of Use

__,_._,___

[Tsinghua-NC] Opening for Full Time Senior / Principal ASIC Design Engineer

Hi,

We have an opening for full time Senior/Principal ASIC Design Engineer.
Here is information about the opening. Please send me your resume
if you are interested.

Job title	Senior / Principal Design Engineer
Location	San Jose, California
Country	USA

Job type	Full Time, Permanent
Job description	Senior / Principal Design Engineer

Low power micro-architecture design techniques are key design point features of the chips we are developing. High quality, low power and low cost are all key design points for our products. Leading edge process technologies such as 65nm and 40nm.

Responsibilities:

Developing the micro-architecture of signal processing/data-path blocks
Implementing design using industry standard tools including RTL coding using verilog, synthesis, DFT and static timing analysis
Working with verification team and backend team to successfully complete chip tape-outs

Qualifications / Requirements:

Masters/Bachelors degree in EE
Knowledge of digital signal processing techniques (design and debug)
Experience with fixed point design and implementation.
Minimum 5 years experience with Verilog ASIC design.
Familiar with RTL verification.
Experience with low power techniques.
Experience with Synthesis and STA tools.

Hongjian

__._,_.___

Reply to sender | Reply to group | Reply via web post | Start a New Topic

Messages in this topic (1)

Recent Activity:

New Members 6

Visit Your Group

MARKETPLACE

Do More for Dogs Group. Connect with other dog owners who do more.

Welcome to Mom Connection! Share stories, news and more with moms like you.

Hobbies & Activities Zone: Find others who share your passions! Explore new interests.

Switch to: Text-Only, Daily Digest • Unsubscribe • Terms of Use

__,_._,___

2010/03/17

[Tsinghua-NC] job opening for contractor

Hi,

We have an opening for a contractor for about 6 months at Synopsys.
Here is information about the opening. Please send me your resume
if you are interested.

Main functionalities: (in this order)
1. Writing recipe – experience on Caliber or Hercules/ICV scripting. Work experience in mask synthesis area of scripting is a big plus.
2. Programming – good in C, knowledge of Python is a plus.

Qualifications:
1. 5+ years of working experience
2. CS/CE/EE background preferred
3. Good geometry manipulation knowledge
4. Experience in either DRC or layer operation area a plus.

Thanks.

Yumin

__._,_.___

Reply to sender | Reply to group | Reply via web post | Start a New Topic

Messages in this topic (1)

Recent Activity:

Visit Your Group

Switch to: Text-Only, Daily Digest • Unsubscribe • Terms of Use

__,_._,___

2010/03/16

[Tsinghua-NC] 关于协助组织常州市新一轮海外领军型人才招聘工作的函 [3 Attachments]

[Attachment(s) from Tsinghua Alumni North Cal included below]

关于协助组织常州市新一轮海外领军型人才招聘工作的函

尊敬的林会长：您好！
    为加快创新型城市建设，促进自主创新和科技创业，根据《常州市新一轮千名海外人才集聚工程实施意见》的有关精神，我市新一轮招聘海外领军型留学归国创业人才的工作已经启动，报名时间从现在开始，全年有效。现将有关招聘公告发给您，请您帮助我们在贵"协会网站"上发布此信息，同时也请您帮助组织和引荐海外人才积极报名参与我市人才引进的招聘工作，我们将不胜感激。

我办是全市人才领导小组成员之一；联络、引进海外人才和留学人员来常州创业、为领军型海归人才服务是我办的基本职能。请报名者在填写《常州市领军型海归创业人才报名表》时（见附件2第4页），在信息获知渠道一栏请填写：常州市人民政府侨务办公室；并填写《常州市侨办引进"领军型海外留学归国创业人才"联系表》（见附件1）之后，传真或电邮至我办，以便我办能为您提供相应的申报服务。

申报的详细情况可登录《常州市千名海外人才集聚工程》网站，（http://www.czhwrc.gov.cn）。
    同时，我们也热忱邀请您来常考察交流，以多种形式在常创新创业，常州市侨办将一如既往地为您做好服务工作。

祝您虎年吉祥、身体健康！

联系单位：常州市人民政府侨务办公室经联处

联系电话/传真：0086-519-85683507

联系人：狄宪成、吴英浩
    电邮／MSN：qiaoban_cz@yahoo.com.cn

常州市人民政府侨务办公室

2010年3月

江苏省常州市人民政府僑務辦公室

The Overseas Chinese Affairs Office Of

Changzhou Municipal Government

中國江蘇常州市龍城大道1280號

No.1280 Longcheng Blvd. Changzhou Jiangsu

郵編 Postal Code:213022

TEL +86 519 85683500
FAX +86 519 85683500

華人華僑相聚龍城

http://czqw.changzhou.gov.cn