[Tsinghua-NC] Digital IC Design Openings at Marvell

Marvell has a couple of immediate digital IC design openings. If interested please send you resume to windysun150@hotmail.com

Opening 1:

Senior Digital IC Design Engineer   •The ideal candidate should have the following qualifications: • BS/MS EE with 3-5 years industrial experience • 4+ years experience in digital circuit design. • Experience in the design of low-power and high-speed digital circuits. • Experience with logic/RTL design – One or more languages knowledge among VHDL, Verilog, System Verilog • Debug skills using tools like ModelSim, VCS, NCSIM, Debussy. • Experience with tools for synthesis and Static Timing Analysis. • Experience with Formal verification tools • Experience in  DFT techniques • Experience in backend implementation flow • Lab Experience w/debug equipment (Oscilloscope, Multimeter, Pattern generators and Logic Analyzer) • Familiarity with FPGA prototyping methodology and concepts Desirable skills: • Good working knowledge of UNIX environment • Good working knowledge of scripting languages (PERL, TCL/Tk) • Ability to work with cross-site teams across the globe We are looking for a motivated engineer who is seeking a challenge in a dynamic company. Responsibilities include: activities such as Model building, RTL vs Model co-simulation, logic design using VHDL/Verilog, synthesis, pre-silicon validation/debug at unit, full-chip verification and Silicon debug. Interface to application engineers, field application engineers, product engineers

Opening 2:

Senior Digital Power Management Design Engineer

Justification 

Digital Design Engineer will work on leading-edge digital controlled power management area. The candidate will simulate, design, implement and verify Marvell's innovated control methodology on AC-DC, DC-DC, and lighting/LED system. The candidate will work closely with the team including system design, analog design, application and test. This opening is the key position in the silicon development of the related products. 

 

 

Job description:

 

The ideal candidate is familiar with digital methodologies with power background and is able to do system level simulation based on power topology and control algorithm. The candidate should be experienced with digital signal processing algorithms and should have solid knowledge of related VLSI architectures. The candidate should be able to implement the control algorithm with the RTL, such as Verilog or VHDL, and be knowledgeable on the mixed-signal systems. The candidate needs to have the background/experience on power electronics, including topology and control.

 

The candidate will work on the digital design on the power management IC, including system level simulation, RTL code implementation and IC verification, help on the front-end and back-end design processes. 

Qualification:

* Experience and Knowledge of the C++, Matlab and Pspice. Being capable of doing the simulation at the system level

* Experience and Knowledge of hardware description languages and experience in behavioral level and RTL coding (Verilog preferred).

* Experience of the FPGA verification of the control algorithm and implementation, such as Xilinx or Altera based system implementation

* Knowledge on power electronics topology, such as Boost, Buck and Flyback, etc., and control methods on AC/DC and DC/DC power management
* Basic knowledge of computer arithmetic, digital signal processing, control theory, and related VLSI architectures.

* BS in Electrical Engineering and at least three years of professional experience, MS and PH.D preferred. For candidates with MS or PH.D degree, less than three years of professional experience would be acceptable.

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