A San Jose based company has several job openings on ASIC analog&
layout design. Please refer to the job description below. Please send
me your resume if you are
interested.
Thanks.
Ann
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1. Analog IC Physical Design (Layout) Engineer
We are looking for an experienced analog IC layout engineer to work
closely with design team to perform physical layout of
high-performance analog and mixed-signal ASICs.
Responsibilities: include block-level layout and verification, top
level routing, floor planning, and tape-out.
Education: At least BSEE or equivalent.
Requirements
Minimum of 2 years analog CMOS layout experience.
Solid understanding of design rules and verification for sub-micron
CMOS processes.
Proficiency in block level floor planning, device matching, parasitic
analysis, buss drop analysis, current density, and isolation
techniques.
Experience with floor planning and integration of top-level designs.
Tape-out experience including final LVS, DRC, ERC, antenna checks,
density checks, and release to fabrication.
Experience with Cadence design environment or similar CAD tools in Unix/Linux.
Effective verbal and written communication skills.
Self-motivated, proactive, and comfortable in a startup environment.
Plus points
Scripting for automation of CAD flow.
Knowledge of digital/SOC CAD flows.
Experience debugging and/or writing DRC and LVS decks.
Analog circuit design experience.
2. Analog IC Design Engineer
We are looking for an experienced analog IC design engineer to work on
the development of mixed ASICs.
Education: At least MSEE or equivalent.
Requirements
Minimum of 5 years analog CMOS design experience in an industrial
environment, covering as many as possible of the following areas: Op
amps, OTAs, comparators, PGAs, Crystal oscillators, Voltage reference
circuits (e.g. bandgap, PTAT,…), Supply voltage regulators, A/D and
D/A converters, Switched capacitor filters, Continuous time filters.
Ability to derive block-level specifications from system requirements.
Experience with Cadence design environment or similar CAD tools in Unix/Linux.
Design for process spread and corner cases.
Design for test and preparation of test specifications.
Good knowledge of ESD and latch-up prevention.
Experience of laboratory characterization of analog ICs.
Experience of taking designs from concept thru to commercialisation.
Effective verbal and written communication skills.
Self-motivated, proactive, and comfortable in a startup environment.
Plus points
Behavioural modelling skills (Matlab, verilog, C, etc)
Scripting for automation of design and verification (Skill, Ocean, Perl,…)
Knowledge of digital/SOC CAD flows.
3. Principle Analog ASIC Engineer
Leads analog design team from concept to product including system
architecture and specification design, circuit and transistor level
design and verification, circuit layout, physical extraction and
verification, silicon bench testing, and production test development.
A qualified candidate must have a EE degree with 10 years of hands-on
analog or mixed signal circuit design experience, with at least 5
years in a design leadership position.
4. Senior ASIC Analog Back End Design Engineer
Responsible from implementation to tape out including floor planning,
layout, place and route, design rule check of mixed signal CMOS ASIC
A qualified candidate must have a EE degree with 5 or more years of
hands-on analog or mixed-signal ASIC implementation and back end flow
experience.
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