Our group has two more immediate open positions. Please forward resume to wding@altera.com.
Thanks,
Weiying
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Job Summary #1:
As a Senior MTS Design Engineer, you will be a key member of a group driving chip level design methodology initiatives. You will need to have a well rounded knowledge of both software and hardware design practices and an understanding of chip level integration processes and flows. This position requires excellent communication skills and the ability to work as part of a team as you will be working with CAD, layout, and Software teams to gather requirements, write up specifications, verify correct implementation, and coordinate multiple methodologies across design teams.
Qualifications:
The successful candidate's minimum qualifications include the following:
• BS in Electrical or Computer Engineering or equivalent with a minimum of 12 years industry experience.
• Knowledge of and hands on experience with system-level custom and ASIC planning, implementation, analysis, and verification flows Expertise in the areas of full chip floorplanning, timing closure, power/metal planning and verification, reliability, and IP integration.
• Excellent communication, teamwork, and problem solving skills.
Job Summary #2:
As a Design Engineer-MTS, you will be a key member of a group driving full chip design and integration. You will help guide other engineers with IP and sub system integration. You will be involved in code reviews to ensure code to define connectivity follows approved guidelines. You will also work with the methodology group to help refine the supported full chip integration flows and maintain the available APIs. This position will require excellent communication skills and the ability to work as part of a team.
Qualifications:
The successful candidate's minimum qualifications will include the following:
BS in Electrical or Computer Engineering or equivalent with a minimum of 8 years of industry experience.
Hands on knowledge for defining design hierarchy and understanding of it's impact to final netlist.
Hands on knowledge and experience of verilog and scripting languages such as TCL, PERL or Python
Knowledge of various netlisting concepts, formats and semantics.
Excellent communication, teamwork, and problem solving skills.
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