[Tsinghua-NC] Job Opening: Senior ASIC design engineer

Dear Alumni,

A silicon valley based bio-sensor company is looking for candidate
that will lead a team of Digital Design Engineers working closely with
Analog Design Engineers developing next generation bio-sensor SoCs.
Please refer to the job description below. Please send me your resume
if you are interested.

Thanks.
Ann

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

Senior ASIC Design Engineer

The ideal candidate must be highly technical hands on and involved
with day to day digital development, from concept through design,
directing the layout, verification, and test.
This candidate will be actively involved in growing and leading the
digital team and working with architect to determine the best
architecture for each product.
This position will design and implement digital functions within mixed
signal ASICs. This position will do both front to back (RTL,
synthesis, verification, mixed mode simulation with the analog
functions, and test support) in bio-sensor mixed ASICs.
As the lead of digital design team, work at all levels of design
including collaborating with system engineer to analyze implementation
tradeoffs and generate detailed specifications, working independently
to propose logic/memory architecture & implementations, doing
sub-block & top level design and simulation, overseeing P & R,
performing timing closure, DFT insertion and bench-tests in silicon.
Backend knowledge is also preferred.
Perform EDA tools installation, foundry design kit setup. Interface
with IP vendors & foundry suppliers to evaluate IP blocks and process
technology.
Assist verification team to design PCB board for chip testing.
Assist in development of production test.
Education Requirements : Master or Ph.D.
Experience Requirements
- Minimum of 10 years digital CMOS design and management experience in
an industrial environment, covering as many as possible of the
following areas:
Embedded processor technologies such as 8051, ARM cores,
Clocking system and power management,
Embedded 1T/6T SRAM and NVM technology,
Embedded DSP block design experience,
Low power management,
Design for test, scan insertion, ATPG, and Functional Test Vectors.
- Experience with Cadence design environment or similar CAD tools in
Unix/Linux.
- Good knowledge of ESD and latch-up prevention.
- Experience of successful multiple tape outs and mass production support.
- Effective verbal and written communication skills.
- Self-motivated, proactive, and comfortable in a startup environment.
Backend experience.
Plus points
Speaking and writing fluency in both Mandarin and English.
Mixed-signal simulation (Cadence AMS) and interfacing with analog
functions is a plus.

------------------------------------

------
Tsinghua Alumni Association of Northern California
Group policy: http://www.tsinghua-nc.org/about/emailYahoo! Groups Links

<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/tsinghua-nc/

<*> Your email settings:
Individual Email | Traditional

<*> To change settings online go to:
http://groups.yahoo.com/group/tsinghua-nc/join
(Yahoo! ID required)

<*> To change settings via email:
tsinghua-nc-digest@yahoogroups.com
tsinghua-nc-fullfeatured@yahoogroups.com

<*> To unsubscribe from this group, send an email to:
tsinghua-nc-unsubscribe@yahoogroups.com

<*> Your use of Yahoo! Groups is subject to:
http://docs.yahoo.com/info/terms/