[Tsinghua-NC] Immediate job opening: MTS: verification architect

Dear alumni and friends,

 

There is an immediate job openning of design verification engineer for the project I am working on.  The company is Altera (ALTR), and the location is in north San Jose. 

 

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MTS: verification architect

 

Scope of position:

As a Senior Level Design Engineer, you will be involved in the verification, silicon check out, and design of Altera's next generation FPGA devices.  You will work as part of a team on the verification and design of Hard IP blocks against a written specification. Your responsibilities will include, but not limited to the following: logic verification planning, architecture, flow/methodology development, system emulation, and silicon debug. You will also provide guidance to a team of junior engineers on advanced verification techniques for high speed/complex digital designs

 

Qualification:

A BSEE/BSCS or equivalent with a minimum of 8 years experience in ASIC verification.  A strong background in ASIC development through the entire design cycle from concept to product release. Prior experiences with the state-of-art verification methogology using SystemVerilog. Prior experiences with high speed serial protocols is desired. Strong communication and written skills are an integral part of this position. A MSEE or PhD is preferred.

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If you are qualified, you can send your resume to me and I will forward  it to the hiring manager. 

 

Good luck.

 

-James

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