My group has a full time intern design engineer opening. The position needs to be filled within couple of weeks.
Scope of Position: This position is responsible for running timing simulations with HSPICE to achieve system level timing closure.
Qualifications: Candidates must have completed at least two years of education toward a BSEE, BSCE or BSCS degree. Good understanding of digital circuit
design and experience in running HSPICE timing simulations are required. Good understanding of static timing analysis methodology is preferred.
If you know anyone who fits this position, please send his/her resume to Weiying@altera.com.
Thanks,
Weiying
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