[Tsinghua-NC] two ASIC Physicl Design engineer opennings

Dear  alumni,

 

 

My group has  a couple of immediate opennings for ASIC physical design engineer from senior to senior staff level.   Here is one job description:

 

 

 

As an ASIC Physical Design Engineer, your main responsibilities will include defining and implementing ASIC backend flows and methodologies; performing block level and chip level physical design, including floorplanning, synthesis, place and route, STA, IR/EM analysis, DRC/LVS; and interfacing with frontend design team, etc.

The successful candidate's minimum qualifications will include the following:

• BSEE or equivalent with a minimum of 6 years of ASIC physical design and methodology experience
• In depth, hands on experience on ASIC design implementation from netlist to GDS using industry standard EDA tools, such as Synopsys IC Compiler or equivalent
• Experience in working with cutting-edge process technology (28nm, 20nm) and taking multiple designs through the complete RTL to GDS flow

·     Experience with low power design, integration of custom IP blocks, large SoC design/implementation

• In addition to being a strong communicator and technical leader, you must be able to drive change across functional teams spanning multiple geographies

 

If you know any people interested in the position, pelase forward resume to me. 

 

The company is Altera  Corporation (ALTR), the location is in north San Jose.

 

Thanks.

James

 

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