Dear Alumni,
My group has openings for Physical Design Engineer with different experience levels. Attached you may find the brief job description and qualification.
Please ask him/her to contact me if you think he/she is qualified.
Cheers,
-Jeffrey
| Qualifications: | * BS/MS in EE/CS with 5+ years of hands-on experience in CAD back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies and deep sub- micron technology issues. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure. * Successful track record of taping out complex SOC chips. * Expert in scripting, solid coding experience in Makefile/Tcl/Tk/Perl. * Self-motivated team worker, good verbal and written communication skills. * Must be a power user of either Synopsys suite (Astro, Apollo, JupiterXT, Physical Compiler, IC Compiler), Magma suite (BlastFusion, BlastPlan), or Cadence suite (First Encounter, Nanoroute). * Solid knowledge of static timing analysis (PrimeTime), EM/IR-Drop/crosstalk analysis (Celtic, PTSI, Apache, AstroRail). * Formal or physical verification (Formality, Verplex, Calibre, Hercules) a plus. |
| Description: | As a key member of central physical design team, you will provide backend design service for multiple Marvell design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna) to backend project management. You will have the opportunity to work on variety of challenging designs, i.e. low power and high speed SOCs. You will work closely with frontend and integration team to ensure successful tapeouts. Your primary responsibility also includes participating in or leading next generation physical design methodology and flow development. |
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