Job Description
As a staff ASIC/SoC Physical Design Engineer, you will be expected to have a strong background of physical design. Your main responsibilities will include defining and implementing backend flows and methodologies; performing IP level and chip level physical design, including floorplanning, place and route, CTS, STA and timing closure ECOs, IR/EM analysis, and physical verification (DRC/LVS); and interfacing with frontend design team.
The successful candidate's minimum qualifications will include the following:
- MSEE or equivalent with a minimum of 10 years of ASIC/SoC design and methodology experience
- In depth, hands on experience on design implementation from netlist to GDS using industry standard EDA tools, such as Synopsys IC Compiler or equivalent
- Experience in working with cutting-edge process technology (45nm or below) and taking multiple designs through the complete netlist2gds flow
- In addition to being a strong communicator and technical leader, you must be able to drive change across functional teams spanning multiple geographies
Please forward your resume to
ningxue2000@yahoo.com --Ning
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