[Tsinghua-NC] two Design Engineer openings (RTL/Synthesis) at Altera San Jose

The front-end design team I support has the following two openings.  If you are interested and qualified, please send your resume to me.  I'll send it to the hiring manager. 

Thanks,
James

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As a Design Engineer, you will be involved in the design and verification of Altera's next generation FPGA devices.  You will work as part of a team on the design of FPGA or Hard IP blocks against a written specification. Your responsibilities will include, but not limited to the following: writing micro-architecture specification, logic design (RTL), and synthesis, timing/power analysis/verification, SOC integration, interfacing with backend team, and silicon debug.

 

Qualification:

 

 

A BSEE/BSCS or equivalent with a minimum of 8 years experience in ASIC development is required. Prior experiences with the state-of-art ASIC design and verification methodologies, logic synthesis, static timing analysis and sign off with deep submicron process technology are required. Deep understanding of cutting edge EDA tools is a must. Strong programming and scripting skills such as Tcl/Perl. Strong communication and written skills are an integral part of this position.

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